Like many others in 2021, Avi Messica and Ziv Leshem saw that scaling down the size of CMOS circuits—the historical driver of Moore’s Law—was reaching the end of its road. “We wanted to do something about it,” says Messica, CEO of Israeli startup NeoLogic. “Since we don’t own a fab we thought of taking a different approach to taking the industry further down the road.”
Their solution will be getting a hard look later this year when the first CPUs built using their new technology are manufactured. Called Quasi-CMOS, the approach uses some elements of a logic scheme last popular in the 1980s to produce designs that should be up to 40 percent smaller and 50 percent more energy efficient than those built using today’s logic.
Quasi-CMOS targets a subset of standard cells, which are the logic and other circuits designed for use in a particular chip manufacturing process. Specifically, it goes after functions that requires six or more inputs. Today’s standard cells can have no more than four inputs, because a greater number would add too much capacitance, which saps speed. Instead, anything needing more than four inputs must have multiple stages of other logic ahead of it, which also slows things down, consumes power, and takes up more space.
“We have single-stage standard cells with 8 to 16 inputs,” says Messica. “This has a profound impact on your entire chip.”
The key to Quasi-CMOS is judicious use of what’s called n-channel metal-oxide semiconductor (NMOS)technology. For decades, CMOS—short for complementary metal-oxide semiconductor—technology has dominated logic chips. For each function, CMOS relies on a pair of transistors, one NMOS and one PMOS (p-channel metal-oxide semiconductor). They are arranged in such a way that they consume very little power unless they are in the act of switching states. CMOS was a huge power savings for CPUs when it was adopted in the 1980s—but it came at the cost of a lot more transistors.
The technology that CMOS replaced, NMOS, is much less power efficient, but with roughly half the number of transistors per cell, input capacitance isn’t as large; so you can have cellswith more inputs than CMOS’s four. According to Messica, the problem with NMOS—besides power consumption—is signal integrity. That is, the output voltage of an NMOS cell can be lower than the input voltage.
Quasi-CMOS combines some NMOS elements with what Messica calls “restoration circuits,” which restore signal integrity to CMOS levels.
Standard cells that would benefit from a larger number of inputs, called high fan-in, can be found all over a processor, but they are particularly important in units that perform math, such as the multiply-and-accumulate systems that GPUs use to accelerate AI, says Messica.
The 15-person company has completed the design of an ARM processor using TSMC’s 16-nanometer process, and the silicon is expected to arrive in December 2024. The company already is at work on standard cells for the leading-edge 5-nm process. And Messica and Leshem’s team plans to produce its own CPU at an advanced node. NeoLogic recently secured US $8 million in funding to continue the work.
The article is reproduced on the website:https://spectrum.ieee.org/stretch-assistive-robot
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